Abstract—A routing-aware architecture is introduced to reduce capture power and peak test power. For shifting of test data or capturing the test responses, only a subset of scan-flip flops are activated in any clock cycle. This process can effectively reduce the capture power and peak test power. In order to reduce routing overhead, two routing driven architectures were proposed. Increase in performance levels were observed in making the proposed scan architecture, more automatic, by automatic shifting of register which requires less number of signals. Results were obtained by experimenting to this proposed scan architecture in reducing capture power, peak test power, test data volume and test application cost.
Index Terms—Power, capture power, peak test power, automatic shift register, test application cost and test data volume.
S. Upadhyayula is with the Jawaharlal Nehru Technological University, Ananthapur, India (e-mail: sangeethaupadhyay@ gmail.com).
Cite: Sangeetha Upadhyayula, "Enhanced Scan in Low Power Scan Testing," International Journal of Modeling and Optimization vol. 2, no. 5, pp. 609-612, 2012.
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