Abstract—ArF immersion lithography has been widely adopted for advanced integrated circuits manufacturing since the 45nm technology node, and now is still one of the mainstream patterning techniques for semiconductor mass production. In this paper, we reported comprehensive evaluation results of a full track tri-layer coating immersion process for 28nm/20nm technology node applications, which included tri-layer process setup and film stack thickness optimization, illumination selection for establishment of printing 45nm line/space (L/S) and 65nm contact hole (CH) patterns. By combination of simulation and experimental verifications, a manufacturable immersion process has been successfully set up and optimized to meet customers’ requirements.
Index Terms—Immersion lithography, process setup, 3D process simulation, line/space, contact hole.
The authors are with the Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research). 2 Fusionopolis Way, #08-02, Innovis, Singapore 138634 (e-mail: wangsh@ime.a-star.edu.sg, liny@ime.a-star.edu.sg, lai-keng-heng@ime.a-star.edu.sg, tanse@ime.a-star.edu.sg, linqy@ime.a-star.edu.sg).
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Cite: Shijie Wang, Ying Lin, Keng Heng Lai, Serene Tan, and Qun Ying Lin, "3D Process Simulation forAdvanced Immersion Lithography," International Journal of Modeling and Optimization vol. 8, no. 3, pp. 193-196, 2018.
